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PI6C410M/410MA
Clock Generator for Intel PCI Express Mobile Chipset
Features
* 14.318 MHz Crystal Input * Selectable of 100, 133, 166, 200, 266, 333, and 400 MHz CPU Output Frequencies * SMBus: Power Management Control * Spread Spectrum support (-0.5% down spread) * Packaging (Pb-free & Green available): -- 56-Pin TSSOP
Description
PI6C410M is a high-speed, low-noise clock generator designed to work with the Intel Mobile PCI Express Chipset. This Spread Spectrum PLL based clock generator reduces EMI emission and supports a wide range of frequencies.
Jitter Performance
* * * * * *
Output Features
* Two Pairs of Differential CPU Clocks * One selectable of CPU/SRC Clock * Seven Pairs of SRC Clocks * Six PCI Clocks * One 48 MHz USB clock * One REF clock * One 96 MHz Differential clock
< 85ps Cycle-to-Cycle CPU 0/1 clock jitter < 125ps Cycle-to-Cycle CPU 2 clock jitter < 350ps Cycle-to-Cycle 48 MHz clock jitter < 500ps Cycle-to-Cycle PCI clock jitter < 125ps Cycle-to-Cycle SRC clock jitter < 1000ps Cycle-to-Cycle REF clock jitter
Skew Performance
* * * *
< 100ps Output-to-output CPU 0/1 clock skew < 150ps Output-to-output CPU 2 clock skew < 500ps Output-to-output PCI clock skew < 250ps Output-to-output SRC clock skew
Block Diagram
XTAL_IN XTAL_OUT SDA SCL
XTAL OSC
Pin Configuration
PLL 2
DOT_96 DOT 96#
/2
SMBus Logic
PLL 1
USB_48 / FS_A REF
PCIF_0 / ITP_EN
USB_48 / FS_A FS_B / TEST_MODE
C O N T R O L
Div
PCI [2:5] PCIF[0:1]
FS_C / TEST_SEL
VTT_PWRGD# / PWRDWN
Div
SRC [0:6] SRC [0:6]# CPU2_ITP / SRC7 CPU2_ITP# / SRC7#
PCI_STOP# CPU_STOP#
Div
CPU[0:1] CPU[0:1]#
VDD_PCI VSS_PCI PCI_3 PCI_4 PCI_5 VSS_PCI VDD_PCI PCIF_0 / ITP_EN PCIF_1 VTT_PWRGD# / PWRDWN VDD_48 USB_48/FS_A VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE SRC_0 SRC_0# SRC_1 SRC_1# VDD_SRC SRC_2 SRC_2# SRC_3 SRC_3# SRC_4 SRC_4# VDD_SRC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PCI_2 PCI_STOP# CPU_STOP# FS_C / TEST_SEL REF VSS_REF XTAL_IN XTAL_OUT VDD_REF SDA SCL VSS_CPU CPU_0 CPU_0# VDD_CPU CPU_1 CPU_1# IREF VSS_A VDD_A CPU2_ITP / SRC7 CPU2_ITP# / SRC7# VDD_SRC SRC_6 SRC_6# SRC_5 SRC_5# VSS_SRC
1
PS8736C
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Pin Description
Pin Name REF XTAL_IN XTAL_OUT CPU[0:1] & CPU[0:1]# SRC[0:6] & SRC[0:6]# CPU2_ITP / SRC_7 & CPU2_ITP# / SRC_7# PCIF_0 / ITP_EN PCIF_1 PCI[2:5] USB_48 / FS_A DOT_96 & DOT_96# PCI_STOP# CPU_STOP# FS_B / TEST_MODE FS_C / TEST_SEL IREF VTT_PWRGD# / PWRDWN SDA SCL VDD_PCI VDD_48 VDD_SRC VDD_CPU VDD_REF VSS_PCI VSS_48 VSS_SRC VSS_CPU VSS_REF VDD_A VSS_A Type Output Input Output Output Output Pin Number 52 50 49 40, 41, 43, 44 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33 35, 36 8 9 3, 4, 5, 56 12 14, 15 55 54 16 53 39 10 47 46 1, 7 11 21, 28, 34 42 48 2, 6 13 29 45 51 37 38 Descriptions 3.3V 14.31818 MHz output 14.31818 MHz crystal input 14.31818 MHz crystal output Differential CPU outputs Differential Serial Reference Clock outputs Selectable Differential CPU or SRC clock output ITP_EN = 0 @ Vtt_Pwrgd# assertion = SRC ITP_EN = 1 @ Vtt_Pwrgd# assertion = CPU 33 MHz clock output / CPU2 select when HIGH 33 MHz clocks outputs (free running) 33 MHz clocks outputs 48 MHz clock output / 3.3V LVTTL inputs for CPU frequency selection 96 MHz differential clock output 3.3V LVTTL active low input for PCI Stop operation. (150k-ohm internal pull-up resistor) 3.3V LVTTL active low input for CPU Stop operation. (150k-ohm internal pull-up resistor) 3.3V LVTTL inputs for CPU frequency selection / Test Mode select: 0 = Hi-Z, 1 = Ref/N 3.3V LVTTL inputs for CPU frequency selection / Test Mode select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW External resistor connection for internal current reference 3.3V LVTTL Level sensitive strobe used to determine to latch the FS_A, FS_B/TEST_MODE, FS_C/TEST_SEL and PCIF0/ITP_EN inputs (active low) / 3.3V LVTTL active high input for Power Down operation. SMBus compatible SDATA SMBus compatible SCLOCK 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs 3.3V Power Supply for PLL Ground for PLL
Output Input / Output Output Output Input / Output Output Input Input Input Input Input Input I/O Input Power Power Power Power Power Ground Ground Ground Ground Ground Power Ground
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Functionality
Frequency Selection(1)
FS_C 1 0 0 0 0 1 1 1 FS_B 0 0 1 1 0 0 1 1 FS_A 1 1 1 0 0 0 0 1 CPU 100 MHz 133 MHz 166 MHz 200 MHz 266 MHz 333 MHz 400 MHz Reserved SRC 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz PCIF / PCI 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz REF 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz DOT_96 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz USB_48 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz
Note: 1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels.
Test Mode Selection(2)
TEST_MODE 1 0
Note: 2. Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
CPU REF/N Hi-Z
SRC REF/N Hi-Z
PCIF / PCI REF/N Hi-Z
REF REF Hi-Z
DOT_96 REF/N Hi-Z
USB_48 REF/N Hi-Z
PWRDWN Functionality
PWRDWN 0 1 CPU Normal Iref x 2 or Float CPU Normal Normal CPU# Normal Float SRC Normal Iref x 2 or Float SRC Normal Iref x 6 or Float SRC# Normal Float PCIF / PCI 33 MHz Low PCIF / PCI 33 MHz Low REF 14.318 MHz Low DOT_96 Normal Iref x 2 or Float DOT_96 Normal Normal DOT_96# Normal Float USB_48 48 MHz Low
PCI_STOP# Functionality
PCI_STOP# 1 0 CPU# Normal Normal SRC# Normal Low REF 14.318 MHz 14.318 MHz DOT_96# Normal Normal USB_48 48 MHz 48 MHz
CPU_STOP# Functionality
CPU_STOP# 1 0 CPU Normal Iref x 6 or Float CPU# Normal Low SRC Normal Normal SRC# Normal Normal PCIF / PCI 33 MHz 33 MHz REF 14.318 MHz 14.318 MHz DOT_96 Normal Normal DOT_96# Normal Normal
PS8736C
USB_48 48 MHz 48 MHz
12/19/05
3
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Serial Data Interface (SMBus)
PI6C410M is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address Assignment
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W I/0
Data Protocol(1)
1 bit Start bit 7 bits Slave Addr 1 R/W 1 Ack 8 bits Register offset 1 Ack 8 bits Byte Count =N 1 Ack 8 bits Data Byte 0 1 Ack 8 bits Data Byte N -1 1 Ack 1 bit Stop bit
Note: 1 Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Data Byte 0: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions SRC_0 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_1 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_2 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_3 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_4 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_5 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_6 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) CPU_2 / SRC_7 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) Type RW RW RW RW RW RW RW RW Power Up Condition 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Output(s) Affected SRC_0 SRC_1 SRC_2 SRC_3 SRC_4 SRC_5 SRC_6 CPU_2 / SRC_7 Pin 17, 18 19, 20 22, 23 24, 25 26, 27 30, 31 32, 33 35, 36 Source Pin NA NA NA NA NA NA NA NA
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 1: Control Register
Bit Descriptions Type Power Up Condition Output(s) Affected Pin 3, 4, 5, 8, 9, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 56 43, 44 40, 41 Source Pin
0
Spread Spectrum 1 = Enable, 0 = Disable CPU_0 output enable 1 = Enabled, 0 = Disabled (Hi-Z) CPU_1 output enable 1 = Enabled, 0 = Disabled (Hi-Z) Reserved REF Output Enable 1 = Enabled, 0 = Disabled USB_48 Output Enable 1 = Enabled, 0 = Disabled DOT_96 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) PCIF_0 Output Enable 1 = Enabled, 0 = Disabled
RW
0 = Spread off
CPU[0:2], SRC[0:7], PCI[2:5], PCIF[0:1]
NA
1 2 3 4 5 6 7
RW RW RW RW RW RW RW
1 = Enabled 1 = Enabled
CPU_0, CPU_0# CPU_1, CPU_1#
NA NA
1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled
REF USB_48 DOT_96 & DOT96# PCIF_O
52 12 14, 15 8
NA NA NA NA
Data Byte 2: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions PCIF_1 Output Enable 1 = Enabled, 0 = Disabled Reserved Reserved Reserved PCI _2 Output Enable 1 = Enabled, 0 = Disabled PCI _3 Output Enable 1 = Enabled, 0 = Disabled PCI _4 Output Enable 1 = Enabled, 0 = Disabled PCI _5 Output Enable 1 = Enabled, 0 = Disabled Type RW RW RW RW RW RW RW RW 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled PCI_2 PCI_3 PCI_4 PCI_5 56 3 4 5 NA NA NA NA Power Up Condition 1 = Enabled Output(s) Affected PCIF_1 Pin 9 Source Pin NA NA
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 3: Control Register
Bit 0 Descriptions SRC_0 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# SRC_1 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# SRC_2 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# SRC_3 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# SRC_4 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# SRC_5 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# SRC_6 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# SRC_7 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# Type RW Power Up Condition 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# Output(s) Affected SRC_0 Pin 17, 18 Source Pin NA
1
RW
SRC_1
19, 20
NA
2
RW
SRC_2
22, 23
NA
3
RW
SRC_3
24, 25
NA
4
RW
SRC_4
26, 27
NA
5
RW
SRC_5
30, 31
NA
6
RW
SRC_6
32, 33
NA
7
RW
SRC_7
35, 36
NA
6
PS8736C
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 4: Control Register
Bit 0 Descriptions CPU_0 Output Control 0 = Free Running, 1 = Stopped with CPU_STOP# CPU_1 Output Control 0 = Free Running, 1 = Stopped with CPU_STOP# CPU_2 Output Control 0 = Free Running, 1 = Stopped with CPU_STOP# PCIF_0 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# PCIF_1 Output Control 0 = Free Running, 1 = Stopped with PCI_STOP# Reserved DOT_Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn Reserved Type RW Power Up Condition 1 = Stopped with CPU_STOP# assertion 1 = Stopped with CPU_STOP# assertion 1 = Stopped with CPU_STOP# assertion 0 = Free running, not affected by PCI_STOP# 0 = Free running, not affected by PCI_STOP# 0 = Driven in power down Output(s) Affected CPU_0 Pin 43, 44 Source Pin NA
1
RW
CPU_1
40, 41
NA
2
RW
CPU_2
35, 36
NA
3
RW
PCIF_0
8
NA
4 5 6 7
RW RW RW RW
PCIF_1
9
NA
DOT_96 & DOT_96#
14, 15
NA
Data Byte 5: Control Register
Bit 0 1 2 3 4 5 6 Descriptions CPU_0 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_1 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_2 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn SRC_Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_0 Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop CPU_1 Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop CPU_2 Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop SRC_Stop drive mode 1 = Hi-Z, 0 = Driven in PCI Stop Type RW RW RW RW RW RW RW Power Up Condition 0 = Driven in power down 0 = Driven in power down 0 = Driven in power down 0 = Driven in power down 0 = Driven in CPU_STOP 0 = Driven in CPU_STOP 0 = Driven in CPU_STOP 0 = Driven in PCI_STOP Output(s) Affected CPU_0 & CPU_0# CPU_1 & CPU_1# CPU_2 & CPU_2# SRC[0:7] & SRC[0:7]# CPU_0 & CPU_0# CPU_1 & CPU_1# CPU_2 & CPU_2# Pin 43, 44 40, 41 35, 36 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 35, 36 43, 44 40, 41 35, 36 17, 18, 19, 20, 22, 23 24, 25, 26, 27, 30, 31 32, 33, 35, 36
PS8736C
Source Pin NA NA NA NA NA NA NA
7
RW
SRC[0:7] & SRC[0:7]#
NA
7
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Data Byte 6: Control Register
Bit Descriptions FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during Vtt_Pwrgd# assertion FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during Vtt_Pwrgd# assertion FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during Vtt_Pwrgd# assertion PCI_Stop control 1 = Disabled, 0 = Enabled, Stopped SRC and PCI clocks REF Output Drive Strength 0 = 1x, 1 = 2x Reserved Test Clock Mode Entry Control 0 = Disabled, 1 = REF/N or Hi-Z Type Power Up Condition Externally Selected Output(s) Affected Pin 35, 36, 40, 41, 43, 44 Source Pin NA
0
R
CPU[0:2]
1
R
Externally Selected
CPU[0:2]
35, 36, 40, 41, 43, 44
NA
2
R
Externally Selected
CPU[0:2] All PCI & SRC clocks except PCIF and SRC clocks set to free-running REF
35, 36, 40, 41, 43, 44 3, 4, 5, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 56 52
NA
3
RW
1 = Disabled
NA
4 5 6
RW RW RW
1 = 2X
NA
0 = Disabled CPU[0:2], SRC[0:7], PCI[2:5], PCIF[0:1], REF, USB_48, DOT_96 3, 4, 5, 8, 9, 12, 14, 15, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 52, 56
7
Test Clock Mode 0 = Hi-Z, 1 = REF/N
RW
0 = Hi-Z
NA
DataByte 7: Control Register
Bit 0 1 2 3 4 5 6 7 Revision Code Vendor ID Descriptions Type R R R R R R R R Power Up Condition 0 0 0 0 1 0 1 0 Output(s) Affected NA NA NA NA NA NA NA NA Pin NA NA NA NA NA NA NA NA
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Vtt_Pwrgd# Timing Diagram
Vcc to VRM 5/12V Vtt FS_A, FS_B, FS_C Vtt_Pwrgd from VRM Vtt_Pwrgd# Vcc Core PwrGood Vcc Clock Gen 0.2-0.3ms Delay State 0 State 1 Wait for Vtt_Pwrgd# State 2 State 3
Clock State Clock Outputs Clock VCO
Off Off
On On
Figure 1. CPU power BEFORE clock power
Vcc to VRM 5/12V Vtt FS_A, FS_B, FS_C Vtt_Pwrgd from VRM Vtt_Pwrgd# Vcc Core PwrGood Vcc Clock Gen 0.2-0.3ms Delay State 0 State 1 Wait for Vtt_P wrgd# State 2 State 3
Clock State Clock Outputs Clock VCO
Off Off
On On
Figure 2. CPU power AFTER clock power
9
PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Clock Power-Up State Machine
S1 Delay >0.25ms Vtt_Pwrgd# = Low S2 Sample Input Straps
Vdda = 2.0V
S0 Power Off
Vdda = Off
S3 Normal Operation Vtt_Pwrgd# = toggle
Enable Outputs
Figure 3. Power-Up State Diagram
Power Down (PWRDWN assertion)
PWRDWN CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz DOT, 96MHz DOT#, 96MHz PCI, 33MHz REF
Figure 4. Power down sequence
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Power Down (PWRDWN De-assertion)
Tstable <1.8ms
PWRDWN CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz DOT, 96MHz DOT#, 96MHz PCI, 33MHz REF
Tdrive_PwrDwn <300us, >200mV
Figure 5. Power down de-assetion
CPU STOP (CPU_STOP# assertation)
CPU_Stop# CPU CPU#
Figure 6. Assertion of CPU_Stop# Waveforms
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset CPU STOP (CPU_STOP# De-assertion)
CPU_Stop# CPU CPU# CPU Internal CPU# Internal Tdrive_CPU_Stop#, 10ns >200mV
Figure 7. CPU_STOP# De-assertion Waveform
PCI STOP (PCI_STOP# assertion)
T SU (10ns min.) PCI_Stop#
PCIF[0:1], 33MHz PCI[2:5], 33MHz SRC, 100MHz SRC#, 100MHz
Figure 8. Assertion of PCI_STOP# Waveform
PCI STOP (PCI_STOP# De-assertion)
T SU (10ns mins.) Tdrive_SRC < 15ns
PCI_Stop# PCIF[0:1], 33MHz PCI[2:5], 33MHz SRC#, 100MHz SRC, 100MHz
Figure 8. De-assertion of PCI_STOP# Waveform
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PS8736C 12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Tristate Specifications
CPU Tristate clock truth table
Signal Pwrdwn pin 0 0 CPU[0:2] 0 1 1 CPU_STOP# pin 1 0 0 X X CPU_Stop Tristate Bit X 0 1 X X Pwrdwn Tristate Bit X X X 0 1 Non-stop Outputs Running Running Running Driven @ Iref x 2 Tristate Stoppable Outputs Running Driven @ Iref x 6 Tristate Driven @ Iref x 2 Tristate
SRC Tristate clock truth table
Signal Pwrdwn pin 0 0 SRC[0:7] 0 1 1 PCI_STOP# pin 1 0 0 X X PCI_Stop Tristate Bit X 0 1 X X Pwrdwn Tristate Bit X X X 0 1 Non-stop Outputs Running Running Running Driven @ Iref x 2 Tristate Stoppable Outputs Running Driven @ Iref x 6 Tristate Driven @ Iref x 2 Tristate
DOT Tristate clock truth table
Signal Pwrdwn pin 0 DOT96 1 1 Pwrdwn Tristate Bit X 0 1 Stoppable Outputs Running Driven @ Iref x 2 Tristate
CPU Clock Tristate Timing
1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable)
DOT DOT#
Figure 10. CPU_STOP = Driven, CPU_PWRDWN = Driven, DOT_PWRDWN = Driven
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset
1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable)
Figure 11. CPU_Stop = Tristate, CPU_PWRDWN = Driven
1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) PU# (Stoppable)
Figure 12. CPU_Stop = Driven, CPU_PWRDWN = Tristate
1.8ms CPU_Stop# PWRDWN CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) DOT DOT#
Figure 13. CPU_STOP = Tristate, CPU_PWRDWN = Tristate, DOT_PWRDWN = Tristate
14
PS8736C
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset
1.8ms PCI_Stop# PCI (Free Running) PWRDWN CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable) 1 PCI clock max
Figure 14. SRC_Stop = Driven, SRC_PWRDWN = Driven
1.8ms PCI_Stop# PCI (Free Running) PWRDWN CPU (Free Running) CPU# (Free Running SRC (Stoppable) SRC# (Stoppable) 1 PCI clock max
Figure 15. SRC_Stop = Tristate, SRC_PWRDWN = Tristate
1.8ms PCI_Stop# PCI (Free Running) PWRDWN CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable)
Figure 16. SRC_STOP = Tristate, SRC_PWRDWN = Tristate, PCI_STOP# = Asserted
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Spread Spectrum Specifications
PI6C410M supports Spread Spectrum clocking and can be enabled and disabled via SMBus control. The maximum Spread Spectrum Modulation is -0.5% down spread with frequency from 30KHz to 33KHz. SSC ON CPU @ 399.000 MHz CPU @ 332.500 MHz CPU @ 266.000 MHz CPU @ 199.500 MHz CPU @ 166.250 MHz CPU @ 133.000 MHz CPU @ 99.750 MHz SRC @ 99.750 MHz PCIF / PCI @ 33.250 MHz Tperiod Min 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 9.997 29.991 Max 2.5133 3.016 3.77 5.0266 6.032 7.54 10.0533 10.0533 30.1598 SSC OFF CPU @ 400.000 MHz CPU @ 333.333 MHz CPU @ 266.666 MHz CPU @ 200.000 MHz CPU @ 166.666 MHz CPU @ 133.333 MHz CPU @ 100.000 MHz SRC @ 100.000 MHz PCIF / PCI @ 33.333 MHz Tperiod Min 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 9.997 29.991 Max 2.5008 3.0009 3.7511 5.0015 6.0018 7.5023 10.003 10.003 30.009 ns Unit
Current-mode output buffer characteristics of CPU, SRC, and DOT
Vdd (3.3V 5%)
Slope ~1/Ro Ro lout
Ros lout 0V 0.85V
Vout = 0.85V Max.
Figure 17. Simplified diagram of a current-mode output buffer
Host Clock Buffer Characteristics
Min RO ROS VOUT 3000 unspecified N/A Max N/A unspecified 850mV
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PS8736C
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PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Cueernt Accuracy
Conditions IOUT VDD = 3.30 5% Configuration Rref = 475 Iref = 2.32mA Load Nominal test load for given configuration Min. -12% x INOMINAL Max. +12% x INOMINAL
Host Clock Output Current
Board Target Trace/Term Z 100 (100 differential 8% coupling ratio) Reference R, Iref = VDD/(3xRr) Rref = 475 Iref = 2.32mA Output Current Ioh = 6 x Iref Voh @ Z 0.7V @ 50
Crystal Recommendations(1)
Frequency 14.31818 MHz Cut AT Loading Parallel Load Cap 20pF Drive Max. 0.1mW Shunt Cap Max. 5pF Motional Cap Max. 0.016pF Tolerance Max. 35ppm Stability Max. 30ppm Aging Max. 5ppm
Note: 1. External trim capacitors (Ce) are required. Ce = 2*CL - (Cs + Ci). Typical Ce = 33pF when Crystal-load = 20pF, Ctrace (Cs) = 2.8pF and CXTAL = 4.5pF.
Absolute Maximum Ratings(1) (Over operating free-air temperature range)
Symbol VDD_A VDD VIH VIL Ts VESD Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage Input High Voltage Input Low Voltage Storage Temperature ESD Protection -0.5 -65 2000 150 C V Min. -0.5 -0.5 Max. 4.6 4.6 4.6 V Units
Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
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PS8736C
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset DC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol VDD_A VDD VIH VIL IIK VIH_FS VIL_FS VOH VOL Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current 3.3V Input High Voltage 3.3V Input Low Voltage 3.3V Output High Voltage 3.3V Output Low Voltage IOH = -1mA IOL = 1mA CPU, SRC, DOT: IOH = 6 x Iref, Iref = 2.32mA IOH Output High Current USB REF, PCI USB IOL Output Low Current REF, PCI Cin Cxtal Cout Lpin IDD ISS ISS Ta Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance Power Supply Current Power Down Current Power Down Current Ambient Temperature VDD = 3.465V, FCPU = 400 MHz Driven outputs Tristate outputs 0 VOH = 1.0V VOH = 3.135V VOH = 1.0V VOH = 3.135V VOL = 1.95V VOL = 0.4V VOL = 1.95V VOL = 0.4V 3 3 30 38 5 6 6 7 500 100 12 70 C mA nH pF 29 27 -33 -33 12.2 15.6 -29 -23 mA 0 < VIN < VDD VDD Condition Min. 3.135 3.135 2.0 VSS - 0.3 -5 0.7 VSS - 0.3 2.4 0.4 Max. 3.465 3.465 VDD + 0.3 0.8 +5 VDD + 0.3 0.35 V A V Units
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PS8736C
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset AC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol Trise / Tfall Trise / Tfall Trise / Tfall Trise / Tfall Tskew Tskew Tskew Tskew Tjitter Tjitter Tjitter Tjitter Tjitter Tjitter Tjitter VHIGH VLOW Vcross Vcross TDC TDC Tstable Tdrive Pwrdwn Trise / Tfall Pwrdwn Outputs CPU, SRC, DOT PCI/PCIF, REF USB CPU, SRC, DOT CPU0, CPU1 CPU2 SRC PCI/PCIF, REF CPU0, CPU1 CPU2 SRC DOT PCI/PCIF USB REF CPU, SRC, DOT CPU, SRC, DOT CPU, SRC, DOT CPU, SRC, DOT CPU, SRC, DOT Parameters Rise and fall Time (measured between 0.175V to 0.525V) Rise and fall Time (measured between 0.8V to 2.0V) Rise and fall Time (measured between 0.8V to 2.0V) Rise and fall Time Variation CPU - CPU Skew CPU - CPU Skew SRC - SRC Skew PCI - PCI Skew / REF - REF Skew (measured at 1.5V) Cycle - Cycle Jitter Cycle - Cycle Jitter Cycle - Cycle Jitter Cycle - Cycle Jitter Cycle - Cycle Jitter (measured at 1.5V) Cycle - Cycle Jitter (measured at 1.5V) Cycle - Cycle Jitter (measured at 1.5V) Voltage HIGH including overshoot Voltage LOW including undershoot Absolute crossing poing voltages Total variation of Vcross over all edges Duty-Cycle 45 45 660 -300 250 550 140 55 55 <1.8 300 5.0 % % ms s ns Fig 2 1,3,6 4, 5 Min. 175 0.5 1.0 Max. 700 2.0 ns 2.0 125 100 200 250 500 85 125 125 250 500 350 1000 1150 mV 1, 2 4 5 4 ps 4 1,3,6 ps 5 1, 2 Units ps Notes 1,2 4
1, 3
REF, USB, PCI/PCIF Duty-Cycle (measured at 1.5V) All clock stabilization from power-up Differential output enable after PwrDwn de-assertion Power down rise and fall time
Notes: 1. Test configuration is Rs = 33.2, Rp = 49.9, and CL = 2pF. 2. Single-Ended measurement. 3. Differential measurement. 4. PCI, PCIF, and REF CL(min) = 10pF, CL(max) = 30pF. 5. USB CL(min) = 10pF, CL(max) = 20pF. 6. CPU measured at 133 MHz.
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PS8736C
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Configuration Test Load Board Termination
Clock Rs = 33 PI6C410M Clock# Rs = 33 Rp = 50 33 Rp = 50 TLB 2pF 2pF TLA
Figure 18. Configuration test load board termination
Note: 1. Maximum 10" trace length for CPU @ 200 MHz, 16" trace for SRC @ 100 MHz.
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PS8736C
12/19/05
PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset Packaging Mechcanical: 56-Pin, 240mil wide, 0.5mm pitch TSSOP (A)

Ordering Information(1,2,3)
Ordering Code PI6C410MA PI6C410MAE PI6C410MAAE PI6C410MAAEX Package Code A A A A Package Description 56-Pin, 240mil wide, 0.5mm pitch TSSOP Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP , Tape and Reel
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. X Suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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PS8736C 12/19/05

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